The present invention relates to an active matrix substrate and a method of making the substrate and also relates to a display device including the active matrix substrate and a method for fabricating the display device.
Recently, liquid crystal display devices (LCDS) have been further broadening their applications. LCDs were normally used indoors as image display devices for desktop computers or TV sets. But now LCDs are often used as video or information display devices for various types of mobile electronic units including cell phones, notebook or laptop computers, portable TV sets, digital cameras and digital camcorders and for car-mounted electronic units like a car navigation system.
Some types of LCDs are addressed using matrix electrodes. Those matrix-addressed LCDs are roughly classifiable into the two categories of passive- and active-matrix-addressed LCDs. In an active-matrix-addressed LCD, pixels are arranged in columns and rows as its name signifies, and each of those pixels is provided with a switching element. And by controlling those switching elements using data and gate lines that are arranged to cross each other, the LCD of this type can supply desired signal charge (i.e., data signal) to a selected one of the pixel electrodes.
Hereinafter, a known active-matrix-addressed LCD will be described with reference to FIGS. 43 and 44. FIG. 43 illustrates a schematic configuration for a known LCD of that type. FIG. 44 illustrates a cross-sectional structure for a typical liquid crystal panel.
As shown in FIG. 43, the LCD includes liquid crystal panel 50 and gate and source drive circuits 51 and 52 with gate and source drivers 53. The panel 50 spatially modulates incoming light. The gate drive circuit 51 selectively drives switching elements in the liquid crystal panel 50, while the source drive circuit 52 supplies a signal to each pixel electrode in the panel 50.
As shown in FIG. 44, the panel 50 includes: a pair of transparent insulating substrates 54 and 55 of glass; a liquid crystal layer 38 interposed between the substrates 54 and 55; and a pair of polarizers 56 placed on the outer surfaces of the substrates 54 and 55. The liquid crystal layer 38 may be a twisted nematic liquid crystal layer, for example.
On the inner surface of the substrate 54 facing the liquid crystal layer 38, pixel electrodes 114 are arranged in matrix. A common transparent electrode 36 is formed on the inner surface of the substrate 55. In this construction, a desired voltage can be applied to a selected part of the liquid crystal layer 38 using the pixel electrodes 114 and common transparent electrode 36. Each of the pixel electrodes 14 is connected to the source drive circuit 52 by way of its associated thin-film transistor (TFT) 110 and data line (not shown in FIG. 44). As shown in FIG. 44, the TFTs 110 are formed on the substrate 54. The switching operation of the TFTs 110 is controllable using gate lines (not shown in FIG. 44, either), which are connected to the gate drive circuit 51 and formed on the substrate 54.
On the inner surface of the substrate 55 facing the liquid crystal layer 38, black matrix 35, R, G and B color filters and common transparent electrode 36 have been formed.
The inner surface of the substrates 54 and 55 facing the liquid crystal layer 38 is covered with an alignment film 37. And in the liquid crystal layer 38, spacers 40 with a size of several xcexcm are dispersed.
The substrate 54 including these members thereon is collectively called an xe2x80x9cactive matrix substratexe2x80x9d, while the substrate 55 with those members thereon is called a xe2x80x9ccounter substratexe2x80x9d.
Hereinafter, various structures for known active matrix substrates will be described.
FIG. 45A illustrates a layout for a unit pixel region defined for a known active matrix substrate, while FIG. 45B illustrates a cross section of the unit pixel region taken along the line A-Axe2x80x2 shown in FIG. 45A.
In the example illustrated in FIGS. 45A and 45B, multiple gate lines 102 and multiple data lines 105 are formed over a glass substrate 121 so as to cross each other. More specifically, the gate lines 102 belong to a first layer on the glass substrate 121, while the data lines 105 belong to a second layer located over the first layer. And the gate and data lines 102 and 105 are electrically isolated from each other by an insulating film 104 belonging to a third intermediate layer between the first and second layers.
In each rectangular region surrounded by the gate and data lines 102 and 105, a pixel electrode 114 has been formed by patterning a transparent conductive film, for example. The pixel electrode 114 receives signal charges from associated one of the data lines 105 by way of a TFT 110 that has been formed near the intersection between the associated data line 105 and one of the gate lines 102. A storage capacitance line 113 has been formed under the pixel electrode 114 to extend parallel to the gate lines 102. Accordingly, a storage capacitance is created between the pixel electrode 114 and storage capacitance line 113.
As shown in FIG. 45B, the TFT 110 includes gate electrode 103, gate insulating film 104, intrinsic (i-) semiconductor layer 106, doped semiconductor layer 107 and source/drain electrodes 108 and 109. The gate electrode 103 is a branch extended vertically from the gate line 102 as shown in FIG. 45A. The gate electrode 103 is covered with the gate insulating film 104. The semiconductor layer 106 is located right over the gate electrode 103 with the gate insulating film 104 interposed therebetween. The doped semiconductor layer 107 exists on the i-semiconductor layer 106. And the source/drain electrodes 108 and 109 are electrically connected to source/drain regions defined in the i-semiconductor layer 106 by way of the doped semiconductor layer 107. As shown in FIG. 45A, the source electrode 108 is a branch extended vertically from the data line 105 and forms part of the data line 105.
The drain electrode 109 is a conductive member that electrically connects the drain region of the TFT 110 and the pixel electrode 114 together. The drain electrode 109, as well as the data lines 105 and source electrode 108, is formed by patterning a metal film. That is to say, in the illustrated example, the data lines 105 and source/drain electrodes 108 and 109 belong to the same layer, and their layout is determined by a mask pattern for use in a photolithographic process.
The source/drain electrodes 108 and 109 are connected together via a channel region defined in the i-semiconductor layer 106. And the electrical continuity of the channel region is controllable by the potential level at the gate electrode 103. Where the TFT 110 is of n-channel type, the TFT 110 can be turned ON by raising the potential level at the gate electrode 103 to the inversion threshold voltage of the transistor 110 or more. Then, the source/drain electrodes 108 and 109 are electrically continuous to each other, thereby allowing charges to be exchanged between the data line 105 and pixel electrode 114.
To operate the TFT 110 properly, at least part of the source/drain electrodes 108 and 109 should overlap with the gate electrode 103. Normally, the gate electrode 103 has a line width of about 10 xcexcm or less. Accordingly, in a photolithographic process for forming the data lines 105 and source/drain electrodes 108 and 109, these members 105, 108 and 109 should be aligned accurately enough with the gate electrode 103 already existing on the substrate 121. Normally, an alignment accuracy required is on the order of xc2x1 several micrometers or even less.
Also, the size of the area where the gate and drain electrodes 103 and 109 overlap with each other defines a gate-drain capacitance Cgd, which is one of key parameters determining the resultant display performance. That is to say, if the gate-drain capacitance Cgd values are not distributed uniformly enough within the substrate plane, then the display quality will deteriorate noticeably. For that reason, the alignment accuracy of an exposure system is controlled at xc2x11 xcexcm or less in an actual manufacturing process to minimize the misalignment.
As can be seen, extremely high alignment accuracy is recently required in making active matrix substrates. To meet that heavy demand, high-precision exposure systems have been developed and actually operated. Before those high-alignment-accuracy exposure systems were available, however, a layout for an active matrix substrate used to be modified in some way or other to increase the alignment margin as much as possible and thereby raise the production yield.
FIG. 46A illustrates a layout that was proposed for an active matrix substrate when exposure systems still had low alignment accuracy. In the arrangement shown in FIG. 46A, the drain electrode 109 of a TFT 110 extends from a pixel electrode 114 parallel to a data line 105 and crosses a gate line 102. The TFT 110 is formed at and around the intersection between the data and gate lines 105 and 102. In the example illustrated in FIGS. 46A and 46B, the gate and data lines 102 and 105 have no branches, the gate line 102 itself serves as a gate electrode and part of the data line 105 serves as a source electrode 108.
An active matrix substrate with this structure is made in the following manner.
First, transparent conductive film 161 and doped semiconductor layer 107 are deposited in this order over a glass substrate 101, and then patterned using a first mask, thereby forming data lines 105, drain electrodes 109 and pixel electrodes 114.
Next, i-semiconductor layer 106, gate insulating film 104 and metal thin film 102 are deposited in this order over the structure prepared in the previous process step. Then, the metal thin film 102, gate insulating film 104 and i-semiconductor layer 106 are sequentially patterned using a second mask, thereby forming gate lines 102 and storage capacitance lines 113 out of the metal thin film 102.
In this method, even if the gate lines 102 are subsequently formed over, and somewhat misaligned with, the data lines 105 and drain electrodes 109 that were formed first, the gate lines 102 still can overlap both the data lines 105 and the drain electrodes 109 in sufficiently large areas. As a result, the unwanted variation in gate-drain capacitance Cgd is suppressible.
In the structure illustrated in FIGS. 46A and 46B, however, the i-semiconductor layer 106 exists in thin stripes under the gate lines 102 and crosses all the data lines 105. Accordingly, when a scan signal (or select signal) is input to one of the gate lines 102 to turn the TFT 110 ON, part of the semiconductor layer 106 located between the drain electrode 109 and the data line 105 on the left-hand side of the drain electrode 109 naturally serves as a channel region for the TFT 110. In addition, another part of the semiconductor layer 106 located between the drain electrode 109 and the data line 105 on the right-hand side of the drain electrode 109 also serves as a channel region for a parasitic transistor unintentionally. In that case, crosstalk should occur between two horizontally adjacent pixels. As a result, the display contrast of an active-matrix-addressed LCD with such a structure, which should be high enough otherwise, decreases disadvantageously.
To solve this problem, an active matrix substrate with the structure shown in FIG. 47 was proposed as disclosed in Japanese Laid-Open Publication No. 61-108171. The active matrix substrate shown in FIG. 47 has basically the same structure as the counterpart shown in FIGS. 45A and 45B. The structure shown in FIG. 47 is different from that shown in FIGS. 45A and 45B in that the gate lines 102 have no branches (i.e., gate electrodes) but that the gate lines 102 themselves serve as gate electrodes in thin stripes. Also, in the structure shown in FIG. 47, the drain electrode 109 extends parallel to the data lines 105. In such a structure, even if the data lines 105 and drain electrode 109 are somewhat misaligned with the gate electrode (i.e., part of the gate line 102), the TFT 110 still can operate properly and the overlap area between the drain electrode 109 and gate line 102 does not change. Consequently, the variation in capacitance Cgd is suppressible.
The structure shown in FIG. 47 can increase the alignment margin up to about 10-20 xcexcm. However, most of the exposure systems currently used for making active matrix substrates realize an alignment accuracy of less than xc2x11 xcexcm. For that reason, the structure shown in FIG. 47 is rarely used now. Instead, the structure shown in FIGS. 45A and 45B is actually adopted much more often to increase the aperture ratio and to make the layout more easily modifiable when failures are found.
In another known type of structure (see Japanese Laid-Open Publication No. 63-279228), pixel electrodes are formed in a layer different from the layer where data lines belong so that the pixel electrodes, formed on an interlevel dielectric film, overlap the data lines. In such a structure, no horizontal gap is needed between the pixel electrodes and data lines because the pixel electrodes are included in a layer located over the layer where the data lines belong. As a result, the pixel electrodes can have their aperture ratio increased and an LCD including such a substrate can have its power dissipation reduced.
Recently, to reduce the weight of electronic units, LCDs fabricated on a plastic substrate, lighter in weight than a glass substrate, are sometimes modeled.
However, the sizes of a plastic substrate are changeable considerably during a fabrication process. Also, any size of a plastic substrate is changeable differently depending on a particular combination of process conditions. So an LCD on a plastic substrate currently operates too much inconsistently to put it to actual use.
A rate at which a plastic substrate changes its size (i.e., expands or shrinks) horizontally to its principal surface (which will be herein referred to as a xe2x80x9csubstrate expandabilityxe2x80x9d) heavily depends on the process temperature or the amount of water absorbed into the plastic substrate. For example, the temperature-dependent expandability of a glass substrate is 3 to 5 ppm/xc2x0 C., while that of a plastic substrate is as much as 50 to 100 ppm/xc2x0 C. Also, a plastic substrate is expandable at as high a rate as 3000 ppm when absorbs water.
The substrate expandability reaching 3000 ppm is the maximum value in all the process steps of the fabrication process thereof. To estimate the mask misalignment actually observable in a photolithographic process, the present inventor modeled TFTs on a plastic substrate and measured how much the substrate was expandable or shrinkable in the interval between two photolithographic process steps that were performed under mutually different combinations of conditions. As a result, I found that the substrate was expandable or shrinkable between the two photolithographic process steps requiring mask alignment at about 500 to 1000 ppm.
If a plastic substrate with a diagonal size of 5 inches is expandable or shrinkable at that high rate, then the size of the substrate is changeable by 64 to 128 xcexcm. And when the substrate size is changeable in such a wide range, no TFTs made by any known method of making an active matrix substrate are operable properly.
I estimated alignment margins allowable by the known structure shown in FIG. 47. FIG. 48 illustrates how an active matrix substrate with the basic structure shown in FIG. 47 should be laid out where an alignment margin, substantially equal to the line width of the data lines 105, is allowed for the substrate. Using this layout, I carried out a computer simulation to obtain substrate expandability that an active matrix substrate with the known structure shown in FIG. 47 and a diagonal size of 5 inches can cope with. The results are as follows:
where the exposure system is supposed to have an alignment accuracy of xc2x10 xcexcm. As shown in Table 1, an active matrix substrate including pixels with a pixel pitch of 250 xcexcm, for example, allows an alignment margin of only xc2x114 xcexcm or less. An active matrix substrate allowing such a narrow alignment margin can barely cope with a substrate expandability of 220 ppm or less.
As can be seen from the foregoing description, none of the known structures allows for preparing an active matrix substrate using a plastic substrate. So there has been no other choice than using a glass substrate with low shock resistance and of a hardly reducible weight for an active matrix substrate.
An object of this invention is to provide (1) an active matrix substrate, which can avoid various misalignment-related problems even if a greatly expandable substrate of plastic, for example, is used as a base substrate for the active matrix substrate and (2) a method of making a substrate of that type.
Another object of this invention is to provide an active matrix substrate in which an array of thin-film transistors has been formed on a plastic substrate.
Still another object of this invention is to provide a display device that has been fabricated using the active matrix substrate of the present invention.
An active matrix substrate according to the present invention includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. Each of the data lines crosses all of the gate lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. In this active matrix substrate, each said pixel electrode and the associated thin-film transistor are connected together by way of a conductive member. And each said pixel electrode crosses one of the gate lines, while the conductive member for the pixel electrode crosses another one of the gate lines that is adjacent to the former gate line.
Another active matrix substrate according to the present invention includes base substrate, gate lines, storage capacitance lines, data lines, thin-film transistors and pixel electrodes. The gate lines and storage capacitance lines are formed on the base substrate. Each of the data lines crosses all of the gate and storage capacitance lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. In this active matrix substrate, each said pixel electrode and the associated thin-film transistor are connected together by way of a conductive member. And each said pixel electrode crosses not only one of the gate lines but also one of the storage capacitance lines, while the conductive member for the pixel electrode crosses not only another one of the gate lines that is adjacent to the former gate line but also another one of the storage capacitance lines that is adjacent to the former storage capacitance line.
Still another active matrix substrate according to the present invention includes base substrate, gate lines, storage capacitance lines, data lines, thin-film transistors, lower-level pixel electrodes and upper-level pixel electrodes. The gate lines and storage capacitance lines are formed on the base substrate. Each of the data lines crosses all of the gate and storage capacitance lines with a first insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the lower-level pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. The upper-level pixel electrodes are located over the lower-level pixel electrodes with a second insulating film interposed therebetween. Each of the upper-level pixel electrodes is associated with, and electrically connectable to, one of the lower-level pixel electrodes by way of an associated contact hole. In this active matrix substrate, each said lower-level pixel electrode and the associated thin-film transistor are connected together by way of a conductive member. The data lines, the conductive members and the lower-level pixel electrodes have all been formed by patterning the same conductive film. And each said lower-level pixel electrode crosses not only one of the gate lines but also one of the storage capacitance lines, while the conductive member for the lower-level pixel electrode crosses not only another one of the gate lines that is adjacent to the former gate line but also another one of the storage capacitance lines that is adjacent to the former storage capacitance line.
Yet another active matrix substrate according to the present invention includes base substrate, gate lines, data lines, thin-film transistors, lower-level pixel electrodes and upper-level pixel electrodes. The gate lines are formed on the base substrate. Each of the data lines crosses all of the gate lines with a first insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the lower-level pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. The upper-level pixel electrodes are located over the lower-level pixel electrodes with a second insulating film interposed therebetween. Each of the upper-level pixel electrodes is associated with, and electrically connectable to, one of the lower-level pixel electrodes by way of an associated contact hole. In this active matrix substrate, each said upper-level pixel electrode and the associated lower-level pixel electrode together makes up a pixel electrode, which is connected to the thin-film transistor, associated with the lower-level pixel electrode, by way of a conductive member. The data lines, the conductive members and the lower-level pixel electrodes have all been formed by patterning the same conductive film. And each said lower-level pixel electrode crosses one of the gate lines, while the conductive member for the lower-level pixel electrode crosses another one of the gate lines that is adjacent to the former gate line.
Yet another active matrix substrate according to the present invention includes base substrate, gate lines, storage capacitance lines, data lines, thin-film transistors, lower-level pixel electrodes and upper-level pixel electrodes. The gate and storage capacitance lines are formed on the base substrate. Each of the data lines crosses all of the gate and storage capacitance lines with a first insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the lower-level pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. The upper-level pixel electrodes are located over the lower-level pixel electrodes with a second insulating film interposed therebetween. Each of the upper-level pixel electrodes is associated with, and electrically connectable to, one of the lower-level pixel electrodes by way of an associated contact hole. In this active matrix substrate, each said upper-level pixel electrode and the associated lower-level pixel electrode together makes up a pixel electrode, which is connected to the thin-film transistor, associated with the lower-level pixel electrode, by way of a conductive member. The data lines, the conductive members and the lower-level pixel electrodes have all been formed by patterning the same conductive film. When one of the gate lines crosses associated ones of the lower-level pixel electrodes, one of the storage capacitance lines, which is adjacent to the gate line, crosses associated ones of the conductive members. On the other hand, when one of the gate lines crosses associated ones of the conductive members, one of the storage capacitance lines, which is adjacent to the gate line, crosses associated ones of the lower-level pixel electrodes.
In one embodiment of the present invention, the active matrix substrate may further include source electrodes, each said source electrode branching from one of the data lines and crossing one of the gate lines. An intersection of each said conductive member with associated one of the gate lines may be located between an intersection of one of the data lines that is closest to the conductive member and the gate line and an intersection of one of the source electrodes that is closest to the conductive member and the gate line.
In another embodiment of the present invention, a distance between each said conductive member and the data line closest to the conductive member may be substantially equal to a distance between the conductive member and the source electrode closest to the conductive member.
In still another embodiment, each said thin-film transistor may have its channel located substantially at the mid-point between two adjacent ones of the data lines.
In yet another embodiment, the channel of each said thin-film transistor may be covered with one of the upper-level pixel electrodes.
In yet another embodiment, a semiconductor layer for each said thin-film transistor may have been self-aligned with the gate line associated with the thin-film transistor. The data lines and associated ones of the conductive members may cross the semiconductor layer.
In yet another embodiment, the data lines and the conductive members may extend across the semiconductor layer. The channel regions in the semiconductor layer may be covered with a channel protective layer that has been self-aligned with the associated gate line.
In yet another embodiment, side faces of the channel protective layer, which are parallel to a direction in which the data lines and the conductive members extend, may be aligned with outer side faces of the data lines and the conductive members.
In yet another embodiment, the other side faces of the channel protective layer, which are parallel to a direction in which the gate lines extend, may be spaced apart from each other by a distance smaller than the line width of the gate lines.
In yet another embodiment, each said conductive member may extend from the pixel electrode, connected to the conductive member, parallel to the data lines. A distance between a far end of the conductive member and an opposite far end of the pixel electrode, connected to the conductive member, may be longer than a pitch of the gate lines but less than twice as long as the gate line pitch.
In yet another embodiment, each of the data lines, the conductive members and the pixel electrodes may include a conductive layer that has been formed by patterning the same conductive film.
In yet another embodiment, each of the data lines, the conductive members and the pixel electrodes may include a transparent conductive layer that has been formed by patterning the same transparent conductive film. An opaque film may cover the transparent conductive layer included in each said data line.
In yet another embodiment, the opaque film may be made of a metal that has an electrical resistivity lower than that of the transparent conductive layer.
In yet another embodiment, in a display area, no parts of the gate and data lines may protrude parallel to the surface of the base substrate.
In yet another embodiment, the gate lines may be made of a metal with opacity.
In yet another embodiment, each said gate line may have a slit-like opening that transmits light at least in respective areas where the thin-film transistors are formed.
In yet another embodiment, each said gate line may be divided into multiple line portions at least in respective areas where the thin-film transistors are formed.
In yet another embodiment, when a negative photosensitive resin layer, which has been formed to cover the gate lines, is partially exposed to light that has been incident thereon through the backside of the base substrate, each said line portion may have such a line width as exposing substantially all of the negative photosensitive resin layer, which is located over the line portion, to the light by utilizing diffraction of the light.
In yet another embodiment, the data lines may be laid out over the base substrate so as to allow the base substrate to expand or shrink less horizontally to the data lines than vertically to the data lines.
In yet another embodiment, the gate lines may be extended beyond the display area, and the extension of each said gate line may have a length greater than the gate line pitch.
In yet another embodiment, color filters may have been formed over the pixel electrodes.
In yet another embodiment, the base substrate may be made of plastic.
In yet another embodiment, the base substrate may include, as an integral part thereof, an optical member for changing the optical path or polarization of incident light.
Yet another active matrix substrate according to the present invention includes plastic substrate, first, second and third gate lines, data line, first and second pixel electrodes and first and second thin-film transistors. The first gate line is formed on the plastic substrate. The second gate line is also formed on the plastic substrate and placed parallel to the first gate line. The third gate line is also formed on the plastic substrate and placed parallel to the second gate line. The data line crosses the first, second and third gate lines with an insulating film interposed therebetween. The first pixel electrode crosses the first gate line, while the second pixel electrode crosses the second gate line. The first thin-film transistor is self-aligned with the second gate line, while the second thin-film transistor is self-aligned with the third gate line. In this active matrix substrate, the first pixel electrode is connected to the first thin-film transistor by way of a first conductive member that crosses the second gate line. The second pixel electrode is connected to the second thin-film transistor by way of a second conductive member that crosses the third gate line.
A display device according to the present invention includes: an active matrix substrate according to any of the embodiments of the present invention; a counter substrate facing the active matrix substrate; and a light modulating layer interposed between the active matrix and counter substrates.
A portable electronic unit according to the present invention includes the display device of the present invention.
An inventive method of making an active matrix substrate includes the steps of: a) forming a plurality of gate lines on a base substrate; b) depositing an insulating film that covers the gate lines; and c) depositing a semiconductor layer over the insulating film. The method further includes the step of d) forming a positive resist layer over the semiconductor layer. The method further includes the step of e) exposing the positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the positive resist layer exposed, thereby defining a first resist mask over the gate lines so that the first resist mask is aligned with the gate lines. The method further includes the step of f) removing parts of the semiconductor layer, which are not covered with the first resist mask, thereby forming a striped semiconductor layer, including portions to be semiconductor regions for thin-film transistors, so that the striped semiconductor layer is self-aligned with the gate lines. The method further includes the steps of: g) removing the first resist mask; and h) depositing a conductive film over the striped semiconductor layer. And the method further includes the step of i) patterning the conductive film using a second resist mask, thereby forming not only a data line and a pixel electrode, which both cross a first one of the gate lines, but also a conductive member, which extends from the pixel electrode parallel to the data line and crosses a second one of the gate lines that is adjacent to the first gate line, and then patterning the striped semiconductor layer, thereby defining the semiconductor regions for the thin-film transistors below the data line and the conductive member.
In one embodiment of the present invention, the step i) may include defining a resist pattern, including relatively thick and relatively thin portions, as the second resist mask. The relatively thick portions will define the data line and the conductive member, while the relatively thin portion will define a region between the data line and the conductive member. The step i) may further include: etching away parts of the conductive film and the striped semiconductor layer that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the conductive film, which has been covered with the relatively thin portion of the resist pattern, thereby forming the data line and the conductive member.
Another inventive method of making an active matrix substrate includes the steps of: a) forming a plurality of gate lines on a base substrate; b) depositing an insulating film that covers the gate lines; and c) depositing a semiconductor layer over the insulating film. The method further includes the step of d) forming a positive resist layer over the semiconductor layer. The method further includes the step of e) exposing the positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the positive resist layer exposed, thereby defining a first resist mask over the gate lines so that the first resist mask is aligned with the gate lines. The method further includes the step of f) removing parts of the semiconductor layer, which are not covered with the first resist mask, thereby forming a striped semiconductor layer, including portions to be semiconductor regions for thin-film transistors, so that the striped semiconductor layer is self-aligned with the gate lines. The method further includes the step of: g) removing the first resist mask. The method further includes the step of h) depositing a transparent conductive film over the striped semiconductor layer; and i) depositing an opaque film over the transparent conductive film. The method further includes the step of j) patterning the opaque and transparent conductive films using a second resist mask, thereby forming not only a data line and a pixel electrode, which both cross a first one of the gate lines, but also a conductive member, which extends from the pixel electrode parallel to the data line and crosses a second one of the gate lines that is adjacent to the first gate line, and then patterning the striped semiconductor layer, thereby defining the semiconductor regions for the thin-film transistors below the data line and the conductive member. The method further includes the step of k) coating the surface of the base substrate with a negative photosensitive resin material. And the method further includes the step of l) exposing the negative photosensitive resin material to light that has been incident thereon through the backside of the base substrate, and then developing the negative photosensitive resin material exposed, thereby removing non-exposed parts of the negative photosensitive resin material and forming a black matrix.
In one embodiment of the present invention, in the step l), parts of the negative photosensitive resin material, which cover the data line, the conductive member and the semiconductor regions for the thin-film transistors, may be exposed to light that passes through areas where the gate lines and the opaque film do not exist, thereby covering an area where the pixel electrode does not exist with the black matrix.
In another embodiment of the present invention, parts of the opaque film, which are not covered with the black matrix, may be etched away, thereby defining a translucent region over the pixel electrode.
In still another embodiment, the step j) may include defining a resist pattern, including relatively thick and relatively thin portions, as the second resist mask. The relatively thick portions will define the data line and the conductive member, while the relatively thin portion will define a region between the data line and the conductive member. The step j) may further include: etching away parts of the opaque film, the transparent conductive film and the striped semiconductor layer that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the opaque film and the transparent conductive film, which has been covered with the relatively thin portion of the resist pattern, thereby forming the data line and the conductive member.
Still another inventive method of making an active matrix substrate includes the steps of: a) forming a plurality of gate lines on a base substrate; b) depositing an insulating film that covers the gate lines; and c) depositing a semiconductor layer over the insulating film. The method further includes the step of d) forming a channel protective layer over the semiconductor layer. The method further includes the step of e) forming a first positive resist layer over the channel protective layer. The method further includes the step of f) exposing the first positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the first positive resist layer exposed, thereby defining a first resist mask over the gate lines so that the first resist mask is aligned with the gate lines. The method further includes the step of g) removing parts of the channel protective layer, which are not covered with the first resist mask, thereby patterning and self-aligning the channel protective layer with the gate lines so that the patterned channel protective layer has a line width narrower than that of the gate lines. The method further includes the steps of: h) depositing a contact layer over the patterned channel protective layer and the semiconductor layer; and i) forming a second positive resist layer over the contact layer. The method further includes the step of j) exposing the second positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the second positive resist layer exposed, thereby defining a second resist mask over the gate lines so that the second resist mask is aligned with the gate lines. The method further includes the step of k) removing parts of the contact and semiconductor layers, which are not covered with the second resist mask, thereby forming a striped contact layer and a striped semiconductor layer, including portions to be semiconductor regions for thin-film transistors, so that the striped contact and semiconductor layers are both self-aligned with the gate lines. The method further includes the steps of: l) removing the second resist mask; and m) depositing a conductive film over the striped contact layer. And the method further includes the step of n) patterning the conductive film using a third resist mask, thereby forming not only a data line and a pixel electrode, which both cross a first one of the gate lines, but also a conductive member, which extends from the pixel electrode parallel to the data line and crosses a second one of the gate lines that is adjacent to the first gate line, and then patterning the striped contact layer, the pattered channel protective layer and the striped semiconductor layer, thereby defining the semiconductor regions for the thin-film transistors below the data line and the conductive member so that the upper surface of the semiconductor regions is partially covered with the patterned channel protective layer.
In one embodiment of the present invention, the step n) may include defining a resist pattern, including relatively thick and relatively thin portions, as the third resist mask. The relatively thick portions will define the data line and the conductive member, while the relatively thin portion will define a region between the data line and the conductive member. The step n) may further include: etching away parts of the conductive film, the striped contact layer, the patterned channel protective layer and the striped semiconductor layer that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the conductive film and contact layer, which has been covered with the relatively thin portion of the resist pattern, thereby forming the data line and the conductive member that are separated from each other.
Yet another inventive method of making an active matrix substrate includes the steps of: a) forming a plurality of gate lines on a base substrate; b) depositing an insulating film that covers the gate lines; and c) depositing a semiconductor layer over the insulating film. The method further includes the step of d) forming a channel protective layer over the semiconductor layer. The method further includes the step of e) forming a positive resist layer over the channel protective layer. The method further includes the step of f) exposing the positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the positive resist layer exposed, thereby defining a first resist mask over the gate lines so that the first resist mask is aligned with the gate lines. The method further includes the step of g) removing parts of the channel protective layer, which are not covered with the first resist mask, thereby patterning and self-aligning the channel protective layer with the gate lines. The method further includes the steps of: h) depositing a contact layer over the patterned channel protective layer and the semiconductor layer; and i) depositing a conductive film over the contact layer. And the method further includes the step of j) patterning the conductive film using a second resist mask, thereby forming not only a data line and a pixel electrode, which both cross a first one of the gate lines, but also a conductive member, which extends from the pixel electrode parallel to the data line and crosses a second one of the gate lines that is adjacent to the first gate line, and then patterning the contact layer, the patterned channel protective layer and the semiconductor layer, thereby defining semiconductor regions for thin-film transistors below the data line and the conductive member so that the upper surface of the semiconductor regions are covered with the patterned channel protective layer.
In one embodiment of the present invention, the step j) may include defining a resist pattern, including relatively thick and relatively thin portions, as the second resist mask. The relatively thick portions will define the data line and the conductive member, while the relatively thin portion will define a region between the data line and the conductive member. The step j) may further include: etching away parts of the conductive film, the contact layer, the patterned channel protective layer and the semiconductor layer that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the conductive film and contact layer, which has been covered with the relatively thin portion of the resist pattern, thereby forming the data line and the conductive member that are separated from each other.
In another embodiment of the present invention, before the contact layer is deposited in the step h), the semiconductor layer may be patterned and self-aligned with the gate lines by exposing the semiconductor layer to light that has been incident thereon through the backside of the base substrate.
In still another embodiment, when the part of the conductive film and contact layer, which has been covered with the relatively thin portion of the resist pattern, is etched away after the relatively thin portion of the resist pattern has been removed, an exposed part of the semiconductor layer may be etched away to leave the semiconductor regions for the thin-film transistors under the patterned channel protective layer.
Yet another inventive method of making an active matrix substrate includes the steps of: a) depositing a semiconductor film over a base substrate; and b) depositing a first conductive film over the semiconductor film. The method further includes the step of c) patterning the first conductive and semiconductor films, thereby forming a plurality of data lines, a plurality of pixel electrodes and a plurality of conductive members so that parts of the semiconductor film, located between each said data line and associated ones of the conductive members, are not removed but left. In this step c), each said conductive member extends from associated one of the pixel electrodes along associated one of the data lines. The method further includes the step of d) depositing an insulating film over the base substrate. The method further includes the step of e) depositing a second conductive film over the insulating film. And the method further includes the step of f) patterning the second conductive film, thereby forming a plurality of gate lines, which cross the data lines, the pixel electrodes and the conductive members, and etching away the parts of the semiconductor film located between each said data line and the associated conductive members entirely except some of the parts of the semiconductor film that are located under the gate lines.
In one embodiment of the present invention, the step c) may include defining a resist mask including relatively thick and relatively thin portions. The relatively thick portions will define the data lines, the pixel electrodes and the conductive members, while each of the relatively thin portions will define a region between associated one of the data lines and associated ones of the conductive members. The step c) may further include: etching away parts of the first conductive and semiconductor films that are not covered with the resist mask; removing the relatively thin portions from the resist mask; and etching away other parts of the first conductive film, which have been covered with the relatively thin portions of the resist mask.
Yet another inventive method of making an active matrix substrate includes the steps of: a) forming a gate electrode on a base substrate; b) forming a gate insulating film that covers the gate electrode; and c) depositing a semiconductor layer over the gate insulating film. The method further includes the step of d) forming a positive resist layer over the semiconductor layer. The method further includes the step of e) exposing the positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the positive resist layer exposed, thereby defining a first resist mask over the gate electrode so that the first resist mask is aligned with the gate electrode. The method further includes the step of f) removing parts of the semiconductor layer, which are not covered with the first resist mask, thereby patterning and self-aligning the semiconductor layer with the gate electrode so that the patterned semiconductor layer includes a semiconductor region for a thin-film transistor. The method further includes the step of g) removing the first resist mask. The method further includes the step of h) depositing a conductive film over the patterned semiconductor layer. And the method further includes the step of i) patterning the conductive film using a second resist mask, thereby forming source and drain electrodes, which both cross the gate electrode, and then further patterning the patterned semiconductor layer, thereby defining the semiconductor region for the thin-film transistor below the source and drain electrodes.
In one embodiment of the present invention, the step i) may include defining a resist pattern, including relatively thick and relatively thin portions, as the second resist mask. The relatively thick portions will define the source and drain electrodes, while the relatively thin portion will define a region between the source and drain electrodes. The step i) may further include: etching away parts of the conductive film and the patterned semiconductor layer that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the conductive film, which has been covered with the relatively thin portion of the resist pattern, thereby forming the source and drain electrodes.
In another embodiment of the present invention, the source electrode may be a part of a data line that extends linearly and crosses the gate electrode, while the drain electrode may extend from a pixel electrode parallel to the data line.
Yet another inventive method of making an active matrix substrate includes the steps of: a) forming a gate electrode on a base substrate; b) forming a gate insulating film that covers the gate electrode; and c) depositing a semiconductor layer over the gate insulating film. The method further includes the step of d) forming a channel protective layer over the semiconductor layer. The method further includes the step of e) forming a first positive resist layer over the channel protective layer. The method further includes the step of f) exposing the first positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the first positive resist layer exposed, thereby defining a first resist mask over the gate electrode so that the first resist mask is aligned with the gate electrode. The method further includes the step of g) removing parts of the channel protective layer, which are not covered with the first resist mask, thereby patterning and self-aligning the channel protective layer with the gate electrode. The method further includes the step of h) depositing a contact layer over the patterned channel protective layer and the semiconductor layer. The method further includes the step of i) defining a second resist mask over the gate electrode. The method further includes the step of j) removing parts of the contact and semiconductor layers, which are not covered with the second resist mask, thereby patterning and self-aligning the contact layer, the patterned channel protective layer and the semiconductor layer, including a portion to be a semiconductor region for a thin-film transistor, with the gate electrode. The method further includes the step of k) removing the second resist mask. The method further includes the step of l) depositing a conductive film over the patterned contact layer. And the method further includes the step of m) patterning the conductive film using a third resist mask, thereby forming source and drain electrodes, which both cross the gate electrode, and further patterning the patterned contact, channel protective and semiconductor layers, thereby defining the semiconductor region for the thin-film transistor below the source and drain electrodes so that the upper surface of the semiconductor region is partially covered with the patterned channel protective layer.
In one embodiment of the present invention, the step m) may include defining a resist pattern, including relatively thick and relatively thin portions, as the third resist mask. The relatively thick portions will define the source and drain electrodes, while the relatively thin portion will define a region between the source and drain electrodes. The step m) may further include: etching away parts of the conductive film and the patterned contact and semiconductor layers that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the conductive film and contact layer, which has been covered with the relatively thin portion of the resist pattern, thereby forming the source and drain electrodes that are separated from each other.
In another embodiment of the present invention, the channel protective layer may be patterned to have a width narrower than that of the semiconductor region.
Yet another inventive method of making an active matrix substrate includes the steps of: a) forming a gate electrode on a base substrate; b) forming a gate insulating film that covers the gate electrode; and c) depositing a semiconductor layer over the gate insulating film. The method further includes the step of d) forming a channel protective layer over the semiconductor layer. The method further includes the step of e) forming a positive resist layer over the channel protective layer. The method further includes the step of f) exposing the positive resist layer to light that has been incident thereon through the backside of the base substrate and then developing the positive resist layer exposed, thereby defining a first resist mask over the gate electrode so that the first resist mask is aligned with the gate electrode. The method further includes the step of g) removing parts of the channel protective layer, which are not covered with the first resist mask, thereby patterning and self-aligning the channel protective layer with the gate electrode. The method further includes the step of h) depositing a contact layer over the patterned channel protective layer and the semiconductor layer. The method further includes the step of i) depositing a conductive film over the contact layer. And the method further includes the step of j) patterning the conductive film using a second resist mask, thereby forming source and drain electrodes, which both cross the gate electrode, and further patterning the contact, channel protective and semiconductor layers, thereby defining a semiconductor region for a thin-film transistor below the source and drain electrodes so that the upper surface of the semiconductor region is partially covered with the patterned channel protective layer.
In one embodiment of the present invention, the step j) may include defining a resist pattern, including relatively thick and relatively thin portions, as the second resist mask. The relatively thick portions will define the source and drain electrodes, while the relatively thin portion will define a region between the source and drain electrodes. The step j) may further include: etching away parts of the conductive film and the contact and semiconductor layers that are not covered with the resist pattern; removing the relatively thin portion from the resist pattern; and etching away another part of the conductive film and contact layer, which has been covered with the relatively thin portion of the resist pattern, thereby forming the source and drain electrodes that are separated from each other.
In another embodiment of the present invention, before the contact layer is deposited in the step h), the semiconductor layer may be patterned and self-aligned with the gate electrode by exposing the semiconductor layer to light that has been incident thereon through the backside of the base substrate.
In still another embodiment, when the part of the conductive film and contact layer, which has been covered with the relatively thin portion of the resist pattern, is etched away after the relatively thin portion of the resist pattern has been removed, an exposed part of the semiconductor layer may be etched away to leave the semiconductor region for the thin-film transistor under the channel protective layer.
A thin-film transistor according to the present invention includes substrate, gate electrode, gate insulating film, semiconductor layer, source electrode and drain electrode. The gate electrode is formed on the substrate. The gate insulating film is formed over the gate electrode. The semiconductor layer is formed over the gate electrode with the gate insulating film interposed therebetween. The source electrode crosses the semiconductor layer. And the drain electrode crosses the semiconductor layer. In this thin-film transistor, side faces of the semiconductor layer, which are parallel to a direction in which the source and drain electrodes extend, are aligned with outer side faces of the source and drain electrodes.
In one embodiment of the present invention, the other side faces of the semiconductor layer, which are parallel to a direction in which the gate electrode extends, may be aligned with side faces of the gate electrode.
In another embodiment of the present invention, a contact layer may exist between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.
Another thin-film transistor according to the present invention includes substrate, gate electrode, gate insulating film, semiconductor layer, channel protective layer, source electrode and drain electrode. The gate electrode is formed on the substrate. The gate insulating film is formed over the gate electrode. The semiconductor layer is formed over the gate electrode with the gate insulating film interposed therebetween. The channel protective layer is formed on the semiconductor layer. The source electrode crosses the channel protective layer. And the drain electrode crosses the channel protective layer. In this thin-film transistor, side faces of the channel protective layer, which are parallel to a direction in which the source and drain electrodes extend, are aligned with outer side faces of the source and drain electrodes.
In one embodiment of the present invention, the other side faces of the channel protective layer, which are parallel to a direction in which the gate electrode extends, may be spaced apart from each other by a distance smaller than the line width of the gate electrode.
In another embodiment of the present invention, side faces of the semiconductor layer, which are parallel to the direction in which the gate electrode extends, may be aligned with the side faces of the gate electrode.
In still another embodiment, the other side faces of the semiconductor layer, which are parallel to the direction in which the source and drain electrodes extend, may be aligned with the outer side faces of the source and drain electrodes.
In yet another embodiment, a contact layer may exist between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer.